1. Field of the Invention
The present invention relates to a burst synchronizing circuit which synchronizes a received data signal in a burst fashion and a sampling phase of the received data signal with each other. More particularly, the present invention is concerned with a burst synchronizing circuit used in an optical subscriber transmission system, in which the received data signal is sampled by a sampling clock synchronized with a stable range of the bit position of the received data signal at the time of receiving the data signal transmitted in the burst fashion as a continuous signal.
2. Description of the Related Art
FIG. 1 is a diagram of an optical subscriber transmission system, which is an example of a system in which a data signal arranged in the burst fashion is transmitted. The optical subscriber transmission system shown in FIG. 1 includes a master station 20-1 and a plurality of slave stations 20-2 (#1-#n), which are coupled with the master station 20-1 via optical fibers 20-3 and an optical coupler 20-4. The slave stations 20-2 correspond to subscribers.
The master station 20-1 continuously transmits a data signal addressed to the slave stations 20-2 (#1-#n) in a down transmission direction. The data signal transmitted in the down transmission direction branches at the optical coupler 20-4, and is transmitted to the slave stations 20-2 (#1-#n) in the broadcasting style. Each of the slave stations 20-2 (#1-#n) discriminates the respective address signal included the data signal transmitted in the down transmission direction, and acquires only the data signal addressed to its own station.
The slave stations 20-2 (#1-#n) transmit data signals to the master station 20-1 in an up transmission direction at respective timings in the burst fashion in order to prevent the data signals from colliding with each other. In this case, the data signal is continuously transmitted in the down transmission direction. Hence, each of the slave stations 20-2 (#1-#n) can perform a retiming operation on the received data signal by using a PLL (Phase-Locked Loop) circuit or the like.
In contrast, the data signals are transmitted in the up transmission direction in the burst fashion. The optical fibers 20-3 become longer as the slave stations 20-2(#1-#n) are located a longer distance away from the master station 20-1. Hence, the master station 20-1 receives the burst signals transmitted by the slave stations 20-2 (#1-#n) at different bit positions and different optical signal levels.
Hence, each time the burst data signal is received, the master station 20-1 is required to select, during a short time, the optimal sampling phase for latching the burst data signal with an appropriate bit phase by using a preamble signal added to the leading end of the burst data signal and to perform the retiming operation on the burst data signal.
FIG. 2 is a block diagram of a burst signal receiving part of the master station 20-1. As shown, the optical burst signal received through the optical fiber 20-3 is converted into an electric signal by an optical module 21-1. The electric signal is then subjected, by a burst synchronizing circuit 21-2, to the retiming operation for latching the data bits of the electric signal with the optimal phase as described above.
Generally, the burst data signal includes a delimiter pattern added to the leading end of the burst data signal in addition to the preamble signal. The delimiter pattern which a data pattern for frame synchronization for identifying the phase of the whole burst signal. A delimiter synchronizing circuit 21-3 performs a delimiter synchronization using a delimiter pattern signal. A data processing part 21-4 processes the received data on the basis of the data signal obtained after the delimiter synchronization.
FIG. 3 is a diagram of a waveform of the output signal of the optical module 21-1 (which is the input signal of the burst synchronizing circuit 21-2). The output signal of the optical module 21-1 has a pulse width which varies due to deterioration of the performance of a built-in optical amplifier and/or deterioration of the S/N ratio. More particularly, A pulse width (a one-bit cycle) T of one time slot has edge-indeterminate areas xcfx84 in the rising and falling edges thereof, as illustrated by dotted areas. The remaining section of the pulse except the edge-indeterminate areas xcfx84 is the valid pulse width within which the sampling can duly be performed. A parameter of how much variations in the pulse width can be tolerated is one of the indexes describing the performance of the burst synchronizing circuit.
FIG. 4 is a block diagram of the conventional burst synchronizing circuit 21-2. An input data signal obtained by converting an optical signal transmitted over an optical fiber into an electric signal is sampled with a plurality of different phases with the period of one bit by a data sampling part 23-1. Thus, the data sampling part 23-1 sequentially outputs pieces of sampled data of the input data signal having mutually different phases.
An edge detecting part 23-2 compares the pieces of sampled data having the neighboring phases with each other, and detects a sampling phase which causes a change of data (the rising or falling edge of the data bit waveform). Based on the detection result obtained by the edge detecting part 23-2, a select signal generating part 23-3 generates a select signal used to select the sampled data obtained by sampling with the optimal phase, and outputs the select signal to a selector 23-4. Then, the selector 23-4 selects the sampled data obtained by sampling with the optimal phase in accordance with the select signal, and outputs it to the next stage.
There are a variety of means, provided in the data sampling part 23-1, for sampling the input data signal with a plurality of different phases with the one-bit period and sequentially outputting pieces of sampled data having the mutually different phases. For example, the input data signal is sequentially delayed at intervals shorter than the one-bit period, and delayed signals are sampled by a system clock (which is a clock having the one-bit period of the input data signal). By way of another example, the input data signal is sampled by a clock faster than the above-mentioned system clock. By way of yet another example, the system clock is sequentially delayed at intervals shorter than the one-bit period, so that multiple phase clocks are generated. Then, the input data signal is sampled by the multiple phase clocks.
There are a variety of means, provided in the edge detecting part 23-2, for detecting the sampling phase which causes a change of data. For example, there is a single-side edge detecting method in which either the rising edge or the falling edge of the signal is detected from the pieces of sampled data having the mutually different phases by means of an edge pattern decoder. There is also a both-side edge detecting method in which both the rising and falling edges of the signal are detected. By way of yet another example, the positions of the edges are detected over a plurality of bit positions and are then averaged, so that the average position can be detected. This method is called a multiple-point edge detecting method.
The single-side edge detecting method detects the phase of the one-side edge of a bit in the input data signal. The above bit is a bit changed from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d, namely, from a low level to a high level, or a bit changed from xe2x80x9c1xe2x80x9d to xe2x80x9c0xe2x80x9d, namely, from the high level to the low level. Then, the sampled data obtained by sampling using the sampling clock after a given timing passing over the section of the related edge-indeterminate area is selected from the phase position of the detected edge.
The both-side edge detecting method detects the phases of the both-sides of a bit in the input data signal. The above bit is a bit which alternately changes to xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, that is, the low and high levels every bit. Then, the sampled data obtained by sampling using the sampling clock located in an intermediate position between the detected edges of the two sides.
FIG. 5 is a diagram of an operation in which the sampled data having the optimal phase is selected by the both-side edge detecting method. More particularly, FIG. 5 illustrates that a data signal 24-1 having values xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d is sequentially input and is sampled by sampling clocks (#1-#14) indicated by ↑. As shown in FIG. 5, sample values xe2x80x9c0xe2x80x9d are obtained by sampling clocks #1-#3, and sampled values xe2x80x9c1xe2x80x9d are obtained by sampling clocks #4-#10. Further, sampled values xe2x80x9c0xe2x80x9d are obtained by sampling clocks #11-#14. Then, it is checked whether the adjacent sampled clocks coincide with each other. Hence, it is possible to detect the edges located between sampling clocks #3 and #4 and between sampling clocks #10 and #11. Then, sampled data is selected by sampling clock #7 having the phase located at the center of the section between the above edges.
The above-mentioned burst synchronizing circuit is described in detail in Japanese Unexamined Patent Application No. 9-83500.
The means for selecting sampled data having the optimal phase by the single-side edge detecting method is not required to transmit a unique data pattern for edge detection. However, the sampling clock located at the fixed timing after the one-side edge of the pulse is always selected. Hence, the sampling clock thus selected does not consider a variation in the phase of the other-side edge of the pulse. Hence, the single-side detection tolerates only a small pulse-width variation.
The means for selecting sampled data having the optimal phase by the both-side edge detecting method selects the sampling phase taken into consideration variations in the phases of the both-side edges of the pulse, and thus tolerates a large pulse-width variation, as compared to the single-side edge detecting method. However, it is necessary to transmit a data signal having a pattern of xe2x80x9c010xe2x80x9d or xe2x80x9c101xe2x80x9d in order to detect the both-side edges of the pulse.
In the normal burst transmission, the preamble added to the leading end of the burst signal is arranged to have an alternating pattern of xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d. The phases of the both-side edges are detected by using the pattern data arranged in the preamble. If a bit error occurs in the alternating pattern, it is no longer possible to detect the both-side edges of one bit but detect the both-side edges over a plurality of bits. Hence, the sampled data having the optimal phase cannot be selected.
The single-side and both-side edge detecting methods select sampled data having the optimal phase by only the one-time edge detection. Hence, there is a possibility that sampled data having an inappropriate phase may be selected in a case where a pulse-width variation over the tolerable level occurs in the input data signal due to deterioration of the S/N ratio.
In contrast, the multiple-point edge detecting method detects the edges of a plurality of bits of the input data signal and has a capability of reducing the influence of bit error. Hence, the multiple-point edge detecting method tolerates a large pulse-width variation, as compared to the single-side and both-side edge detecting methods. However, the multiple-point edge detecting method requires a plurality of data bits to be acquired and thus a longer time necessary to select the sampled data having the optimal phase.
An object of the present invention is to provide a burst synchronizing circuit in which the above disadvantages are eliminated.
A more specific object of the present invention is to provide a burst synchronizing circuit having a tolerance for pulse-width variation as large as the both-side edge detecting method without any bit-basis alternating pattern for burst synchronization and having a capability such that sample data having the optimal phase can be selected for a short time even if a bit error occurs.
The above objects of the present invention are achieved by a burst synchronizing circuit which synchronizes a received data signal in a burst fashion and sampling phases with which the received data signal is sampled, said burst synchronizing circuit comprising: a first part which samples a data pattern with different sampling phases; and a second part which selects the received data signal sampled with an optimal sampling phase based on sampling phases with which the pattern data is detected.